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All version of these documents are uncontrolled and for Reference only.

 

 


Today's designs are using BGA technology or are rapidly heading in that direction. Most of the major chip manufacturers are changing even long time QFP packaging over to BGA technology. Component density will dictate the PCB technology, packaging shrinks and requires tighter geometries.

Benefits of BGA's

• Higher I/O Capacity

• Smaller Foot Print and Package Size

• Increase functionality

• Enhanced Signal and Thermal Performance

• Easier Assembly as opposed to QFP with same I/O Capacity resulting in higher first pass yield.

Fine pitch devices today require a flat planar surface finish. Alternatives to Hot Air Solder Level (HASL) may be required to provide reliable component placement. Some alternatives are price competitive to HASL and will provide the planar surface finish required for Fine Pitch BGA assembly. Click this link for Additional information regarding Alternative Surface Finishes.

CONSIDERATION
Trace Width (Inches)
Copper Thickness (Inches)
Copper Thickness(Ounce)
> 0.0045
0.0014
1 oz.
0.0045 - .003
0.0007
1/2 oz.
< .003
.00035
1/4 oz

Density of the design will dictate the needed geometry. Copper thickness will be an item to consider when addressing finer trace widths and spacing. Advanced technology will limit your supplier base. Specific Geometries that are required for most sub 1mm pitch BGA routing will require trace widths and spacing less then 0.005 inches.

VIA IN PAD TECHNOLOGY
VIA IN PAD
Before
After
Via in Pad Before After Standard BGA Via & land Technology (Dog Bone Pattern)
Conductive Fill Via BGA Land

Via In Pad Technology is used to open up routing channels on the surface of the board. Holes are drilled into the center of the SMT pad and then plated, filled with a thermal set epoxy based material, to provide a smooth surface.

DESIGN CONSTRAINTS
Device Pitch MM
A Pitch (Inches)
B Solder Pad (Inches)
C Via Pad/Drill (Inches)
1.50
0.059
0.030
0.025 / 0.013
1.27
0.050
0.0285
0.023 / 0.012
1.00
0.0394
0.027
0.020 / 0.010
0.80 0.0315 0.016 0.019 / 0.009
0.75 0.0256 0.014 0.018 / 0.006
0.65 0.0256 0.012 Micro Via
0.50
0.0197
0.011
 Micro Via
INNER LAYER
Device Pitch MM
D Pitch (Inches)
E Pads / Drill (Inches)
F Single Trace (Inches)
G Pairs Trace (Inches)
G Pairs Space (Inches)
1.50
0.059
0.025 / 0.013
0.012
0.006
0.007
1.27
0.050
0.023 / 0.012
0.010
0.005
0.005
1.00
0.0394
0.0194 / 0.009
0.008
0.004
0.004
0.80
0.0315
0.0165 / 0.0065
0.0195 / 0.0095
0.005
0.004
0.003
N/A
0.003
N/A
0.75 0.0295 0.0175 / 0.007
0.0145 / 0.006		 0.004
0.005		 N/A
0.003		 N/A
0.003
0.65

0.0256
Micro Via
0.003
N/A
N/A
0.50
0.0197
Micro Via
0.003
N/A
N/A

Necking down traces as they rout into the BGA is a common practice when trace widths are less then 0.004 inches. This allows the remainder of the routed signals to use standard trace and space geometry. With this practice you can increase the manufacturability of the design and ensure better yields.

 

 

INTERNAL PLANE LAYERS

 

 

 

 

 

As component pitch becomes smaller or densities increase a common problem is isolation of plane tie connection and or a reduction of copper to the tie which may cause performance issues. When designing copper between clearances a minimum value of 0.006" for 1 oz copper and 0.005" for 1/2 oz copper is recommended. This will ensure that the connection is not broken during the etching process.

Remove thermal connection on fine pitch devices. This will allow the hole to drill directly into the plane and avoid additional pin isolation by the thermal pad.

VIA PLUG
 

 

A common issue with BGA assembly is the potential of contaminates wicking up through the via and causing problems under the BGA during the primary or secondary assembly process. To prevent this DCS has a Via Plug Process that allows encapsulation of the hole and prevent foreign material from passing through the via and effecting the assembled solder joint under the BGA.

 

MASK DEFINED SMT LAND
Many customers have asked if we can provide a mask defined land location. This process defines the solder mask clearance smaller then the surface land. Typical overlap would be .002 - .005 inches. The reliability of this type of solder joint is still in review. Most recommendations are that a clearance around the pad allows the solder ball to adhere to the surface and the edge of the pad allowing a better solder joint lock down. DCS offers both capabilities to ensure the specific technique is supported.
ELECTRICAL TEST LIMITATIONS
Due to component density test charges for fixture tests may be more expensive than standard technology. The reason for this advance test technology is the total number of test locations on the machine in relationship to the required amount for the BGA chip. Often the outer most points are difficult to test due to pin deflection. To resolve this problem, DCS offers State-of-the-Art Flying Probe test. This will eliminate Test Fixture cost and provide a high density netlist test for every board.

© 1997 Data Circuit Systems Inc. All Contents and Graphics are the sole property of Data Circuit Systems, Inc. and can not be reused or distributed without the written approval from Data Circuit Systems, Inc. All version of these documents are uncontrolled and for Reference only. If you have suggestions or comments on content, please direct to: webmaster@datacircuits.com Last Modified: 03/13/2003

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